Semiconductor integrated circuits have substantially increased in density in the past decade. However, there is an increasing demand for higher levels of integration, higher switching speeds and smaller devices for new applications, such as microprocessors and minicomputers. The field effect transistor technology is dominant in main memory and lower performance logic and arrays because of its higher circuit density and simpler processing as compared with bipolar technology.
A very active area in the semiconductor fabrication technology has been the generation and application of fine lines and line separations in the lithographic technology. Light had been used almost exclusively until the recent past in the lithographic process for exposing a photosensitive film. However, optical resolution limits make further advances in finer line widths and line separations much more difficult. The most important and versatile among the technologies for the future reduction in line widths and separations are electron beam and X-ray exposure processes. The lithography problems and their possible solutions are discussed in greater detail by D. L. Critchlow in the publication entitled "High Speed MOSFET Circuits Using Advanced Lithography", published in the Computer, Vol. 9, No. 2, February 1976, pp. 31 through 37. In that publication the substantial equipment costs and complexities of X-ray and electron beam lithography are described.
There have been alternative efforts to obtain narrow line widths and separations in the range of one micrometer or less by extending standard photolithography techniques and avoiding the need for the more expensive and complex techniques, such as electron beam or X-ray lithography. One such technique is described by H. B. Pogge in IBM Technical Disclosure Bulletin, November 1976, Vol. No. 6, entitled "Narrow Line Widths Masking Method". This method involves the use of a porous silicon followed by oxidation of porous silicon. Another technique is described by S. A. Abbas, et al, IBM Technical Disclosure Bulletin Vol. 20, No. 4, September 1977, pp. 1376 through 1378. This TDB describes the use of polycrystalline silicon masking layers which are made into masks by first using an intermediate mask of oxidation blocking material, such as silicon nitride in the formation of the polycrystalline silicon. Line dimensions below about two micrometers may be obtained by this technique. T. N. Jackson, et al, described "A Novel Sub-micron Fabrication Technique" in the March 1980 publication Semiconductor International, pp. 77 through 83. This method for producing sub-micron line widths and devices does not require electron beam lithography but used a selective edge plating technique. The U.K. Pat. No. 2,003,660 published Mar. 14, 1979 describes a method for depositing an area of metal, for example metal on a substrate and forming narrow metal stripes by using a unidirectional plasma etching technique. K. H. Nicholas, U.S. Pat No. 4,083,098 describes a method of making a plurality of closely spaced, but air isolated, conductive layers on an insulated substrate. He suggests no ohmic connections to the silicon body under the insulator supporting his conductive layers. The above techniques do show ways of forming narrow lines on substrates but lack an overall solution for their successful use in the manufacture of semiconductor devices, because it is unclear how they will be used to contact actual device elements within the semiconductor substrate in an accurate and effective manner. Further, there are problems of planarity of the first level metallurgy and adequate conductivity of the metallurgy at that level.
The patent application of H. B. Pogge, Ser. No. 957,604 filed Nov. 3, 1978, entitled "Method for Forming a Narrow Dimensioned Region on A Body", now U.S. Pat. No. 4,256,514 and the patent application of J. Riseman Ser. No. 957,606 filed Nov. 3, 1978, entitled "Method for Forming An Insulator Between Layers of Conductive Material", now U.S. Pat. No. 4,234,362 describe techniques for forming narrow dimensioned, for example submicron regions on a semiconductor body that involves forming on the silicon body regions having substantially horizontal surfaces and substantially vertical surfaces. A layer of a very narrow dimension is formed both on the substantially horizontal and substantially vertical surfaces. Reactive ion etching is applied to the layer to substantially remove the horizontal layer while leaving the vertical layer substantially intact. The vertical layer dimension is adjusted depending upon the original thickness of the layer applied. The patent applications more importantly describe techniques for using this narrowed dimensioned region in a semiconductor device fabrication process for various types of integrated circuit structures such as field effect devices.
A major problem in very dense integrated circuits is the electrical contacts to the various elements and devices in the semiconductor integrated circuits. A problem involves the conductivity of the metallurgy at the various levels as the device density increases. In recent times, solutions to these problems have taken the direction of the use of highly doped polycrystalline silicon as conductive layers such as shown in R. C. Wang, U.S. Pat. No. 3,750,268, issued Aug. 7, 1973 and R. T. Simko, et al U.S. Pat. No. 3,984,822, issued Oct. 5, 1976. However, as the density of devices has increased, there still remain problems involving isolation between devices, conductivity particularly at the first level of metallurgy contacting the semiconductor devices, and alignment of the levels of metallurgy to the device elements in the semiconductor integrated circuit.
In the usual methods for forming double polycrystalline silicon multilayer structures, silicon dioxide is used as the insulator between the layers. The silicon dioxide thickness between two polycrystalline layers is normally directly related to the thickness of the silicon gate oxide where a FET type device is being made. The usual thermal oxidation techniques are used to form the silicon dioxide layer.
It is the object of this invention to provide methods for forming an insulator of any desired thickness between the conductive layers, which are polycrystalline silicon for the gate electrodes and metal for other purposes, and, in particular, on the vertical regions between the layers of conductive material which are the electrical contacts to elements of field effect transistor integrated circuits.
The method for forming FET integrated circuits having a pattern of narrow dimensioned dielectric regions on the body of a monocrystalline semiconductor, preferably silicon, involves providing the silicon body and forming a first insulating layer on a major surface of the body. A highly doped polycrystalline silicon layer and a silicon nitride layer are then successively formed on the first insulating layer. Openings in the silicon nitride and polycrystalline layers are made using directional reactive ion etching which results in a structure having substantially horizontal surfaces and substantially vertical surfaces. The openings are in those areas designated to be the gate regions of the field effect transistors in the integrated circuit. A second insulating layer is then deposited on both said substantially horizontal surfaces and said substantially vertical surfaces. The thickness of the second insulator layer is the desired thickness of the narrowed dimensioned dielectric regions to be ultimately formed on the semiconductor, or preferably silicon body. The structure is placed in a vertically directional reactive ion etching ambient where the second insulating layer is substantially removed from the horizontal surfaces. This directional etching has no significant effect on the insulating layer on the vertical regions of the polycrystalline silicon. The semiconductor body is subjected to a heat cycle to suitably drive down the dopant from the polycrystalline silicon layer into the semiconductor body in intimate contact with the polycrystalline silicon layer. The gate dielectric layer is formed. A second doped layer of polycrystalline layer is obtained and a plastic layer, such as polyimide or photoresist, is coated over it. The second polycrystalline silicon layer and the plastic layer are etched at practically the same etch rate using reactive ion etching until the silicon nitride layer is exposed. Patterns are formed in the remaining second polycrystalline layer, and a silicon dioxide layer is thermally grown at the surface of the second polycrystalline silicon layer. The exposed silicon nitride and first polycrystalline silicon regions are then removed by etching to leave the self-standing narrow dimensioned dielectric regions on the silicon body surface. Using a non-critical mask, portions of the silicon dioxide layer covering the second polycrystalline silicon and portions of the narrow dimensioned dielectric regions are removed in areas away from the FET areas. A conductive layer of one or more wide variety of possible materials is now deposited using a lift-off mask upon the narrow dimensioned regions and on the silicon body to make contact to source/drain PN regions. Where the conductive layer is formed upon bare silicon, ohmic contacts can be formed thereto. A plastic material, such as a polyimide or photoresist, is deposited over this conductive layer to planarize the surface thereof. The structure is then placed in a reactive ion etching ambient where the conductive layer is uniformly etched together with the plastic layer until the tops of the narrow dimensioned regions are reached. The remaining plastic material is then removed to thereby form the substantially planar conductive layer with narrow dimensioned dielectric isolation separating portions of the conductive layer from other portions of the conductive layer and the polycrystalline silicon gate electrode.
The method can be used to form a variety of field effect transistor products. These structures are formed by appropriate modifications of the method described in the preceding paragraph to form suitable PN junctions, gate dielectric and electrode structures, PN contact regions, together with openings to the semiconductor body which have these elements formed therein. Logic and memory field effect transistor integrated circuits may be formed according to these methods to provide the beneficial results of high density with suitable conductivity of the metallurgy layers and good planarity, with its attendant yield and reliability.
The method may be adapted to form a short channel field effect transistor integrated circuit. This structure includes a silicon body having a pattern of narrow dimensioned dielectric regions on a major surface of said body. A gate dielectric layer is located on the major surface between certain portions of the narrow dimensioned regions. PN junction source/drain regions are located directly below certain portions of the narrow dimensioned regions and associated with a short channel under said gate dielectric layer. Polycrystalline silicon gate electrodes are located on the surface of the gate dielectric layer between certain of the narrow dimensioned regions. Metal electrical contacts are made to the edges of said PN junction regions while filling the spaces between the remaining narrow dimensioned regions. These contacts are self-aligned to the narrow dimensioned regions and substantially planar with the tops of the narrow dimensioned regions.